Show HN: Write, simulate and synthesize VHDL/Verilog in the browser

The problem I wanted to solve: one of the barricades for the beginners learning hardware design is having to spend an entire evening setting up EDA tools, just to see a single waveform. A lot of beginners will give up fairly quickly before even getting to writing any code. I decided to make it easier for them and build a browser-based IDE. RisingEdge lets you write VHDL or SystemVerilog, run a simulation, see the waveform, and even check what the code actually synthesizes into. Everything is built with real open-source tools (GHDL, Icarus Verilog, Yosys).

I put a lot of effort into making the synthesis view good for new learners. You can see a gate level netlist with cell counts, a block level view highlighting the code that produced the block, and even auto-generated state machine diagrams to make debug easier.

There are 3 separate ways to use the tool: - Learn: a full course from Fundamentals to Advanced, over 100 lessons, examples, and exercises each - Practice: over 50 challenges built to sound like real-world engineering tasks - Playground: lets you run any arbitrary RTL if you want to try things out or just see what it synthesizes into

Most of the content is free with no account: the entire Practice section, the Playground, and the Fundamentals section of the curriculum. The only paid thing is the full course - and it's billed as a single non-recurring payment.

Happy to answer any questions!