Demystifying DRAM Read Disturbance: RowHammer and RowPress Phenomena

mikewarot•about 1 hour ago

It's my long standing opinion[1] that we shouldn't accept any RAM that can be subject to random bit flips. Most of the mitigations are just security through obscurity.

[1] https://news.ycombinator.com/item?id=33860477

inigyou•29 minutes ago

My computer with a lot of ECC DDR5 sometimes catches several bitflips in a day. I know this because they are reported to dmesg and sometimes I look at dmesg.

Intel decided long ago that you would need to pay more to not be subject to random bitflips. So it's an AMD system.

e2le•about 1 hour ago

I was shocked to learn that around 10% of Firefox crashes are caused by bit flips.

https://news.ycombinator.com/item?id=47252971

inigyou•31 minutes ago

Most software is like this. Factorio had a weird one where some routers dropped UDP packets with zero checksum.

Retr0id•about 1 hour ago

Intel MEE addressed this (https://eprint.iacr.org/2016/204.pdf), by treating DRAM as entirely untrusted (assuming an attacker with arbitrary physical read/write capabilities), but then they discontinued it.

Regarding your linked comment:

> If we had properly tested and validated RAM, RowHammer wouldn't work, ever.

While it's exacerbated by physical defects and tight timings, it's really a fundamental problem with how DRAM works. It's frankly a miracle it works in the first place.

inigyou•30 minutes ago

No. If it was designed really well, it would trigger extra refreshes as needed. It would know how much accessing a row disturbs nearby rows and how much disturbance a row can suffer before it needs a refresh to prevent data corruption. It would know how long a row can be held open for, too. There is no fundamental theorem that rowhammer must work. It was an engineering tradeoff.

I don't think we can blame DRAM designers for flying a teensy bit too close to the sun here, since this is no problem in normal operation and only appears under adversarial scenarios. We can blame them for not fixing it once it was discovered. And we can definitely blame Intel for making ECC RAM a market segmentation feature.

Retr0id•19 minutes ago

What you describe is the Target Row Refresh (TRR) mitigation, and it can be bypassed via "half-double" attack.

Demystifying DRAM Read Disturbance: RowHammer and RowPress Phenomena

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