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Discussion (119 Comments)Read Original on HackerNews
The only real point of contention I see between the two is that this piece goes on to talk about how it's a selling point that RISC-V can be used for both low-end 10 cent microcontrollers, and high-end multi-core processors running Linux. Personally I don't see the benefit of this since you're going to have to recompile your software anyway, and since all the RISC-V SBCs I'm aware of have significantly worse performance and efficiency than comparably priced ARM SBCs.
Dmitry is talking about high-end application processors that you might find in a mid-range or better laptop, smartphone or server. Armstrong Subero seems to think that anything larger than a "dirt cheap microcontroller" is high-end.
People shouldn't take this the wrong way, but the VexRISC-V cores in Baochip are not "high-end". They are basically as low-end as you can get while still meeting the modern definition of "application core". And that doesn't matter, because being high-end application SoC is not Baochip's design criteria. These cores are actually pretty decent for Baochip's criteria.
The VexRISC-V are implementing the exact style of "classic-RISC" microarchitecture that RISC-V is optimised for. It's basically the optimal niche for RISC-V, before any of the problems start showing up.
And RISC-V is just starting here with shoestring design and fab budget. Wait till all engineering teams really adopt it like Tenstorrent and NextSilicon and so on.
Any examples of this?
* Tenstorrent Ascalon has a neat optimization for certain LMUL>1 SIMD operations. LMUL=2 effectively unrolls the SIMD operation making it read two SIMD registers from every source and write two SIMD registers to the destination. There are however some instructions where LMUL=2 only needs to write to one registers, those are narrowing instructions (e.g. 64-bit to 32-bit truncation) and comparisons (which write to a LMUL=1 register with packed bits). When those SIMD instructions have to .vx form, which means one argument comes from a GPR, they now only need to write one SIMD register and need to read two SIMD registers. This matches what regular SIMD instructions need and because the silicon for the execution is much cheaper than register file ports, Ascalon can exexute these instructions in a single operation. So you can compare twice as many SIMD elements against a scalar, then you can against another SIMD register.
* Ventana (now under Qualcomm) talked a tiny bit about their fetch-block-optimizer and something that sounded like a L1i-trace cache. The fetch-block-optimizer would go to certain hot L1i entries and "optimize" them, with agressive instruction fusion including fusion of non-adjacent instructions.
* NextSilicon: Idk any details yet, but they said they handled RVC without increasing latency and that they've found a good solution for implement RVV and especially LMUL, which is a challange in out-of-order designs.
* OpenXiangShan: The fastes open-source CPU, is working on doing 2-ahead instruction fetch (the thing Zen5 added).
Now that being said, Ventana was bought by Qualcomm, we know the RISC-V team is still alive, but who knows if we'll ever see anything from that outside of Qualcomm?
The Tenstorrent Ascalon devboard is way behind schedule and on 12nm TSMC instead of a 4nm node the processor was designed for and is now supposed to clock at 1.38GHz. Though I think the delay has more to do with TT management problems then with the actual design.
While the scalar part of OpenXiangShan looks really good, the RVV imolementation is currently basically unusable. They want to have fix for the problems until the end of the year, but we'll have to see.
The improvement is entirely "we don't have to pay ARM"
I assume this is addressing
> and since all the RISC-V SBCs I'm aware of have significantly worse performance and efficiency than comparably priced ARM SBCs.
If so, could you point at specific SBCs that beat ARM SBC perf?
The benefit is a unified toolchain. Make a chip, get the entire software toolchain for free.
In the past if you made your own chip you had to write your own assembler, compiler, debugger, etc. Many manufacturers forked gcc but of course it's still a lot of work and the license isn't great (for them, not the user).
This universal compiler toolchain is massive benefit for both the chip makers and the end user.
So it is with the family of mutually incomprehensible ISAs called RISC-V.
I don't get how both things can be true. The cost to ship something to Trinidad and Tobago has nothing to do with whether it's ARM or RISC-V; shipping the same weight of either kind of chips should cost exactly the same amount. Yes, maybe the chip cost itself of a particular ARM-based model is $0.15 while the equivalent RISC-V chip costs $0.10, but if the issue (for him and other people who live outside US/Europe) is that shipping costs are orders of magnitude more expensive than the thing being shipped, that chip-cost difference becomes irrelevant.
I think he does make a great point about how fragmentation does give you better optionality: ARM is sort of like cable TV where you have a small number of product categories that each bundle a particular set of features, whereas with RISC-V you design something bespoke that does exactly what you need and nothing more. But again, this isn't going to affect shipping costs.
Aliexpress doesn't do any ID verification hassle. This is all an argument more about distribution and shipping. RISK-V is going to win because getting the parts is insanely cheap and without overhead.
The "fix" is probably Digikey, Mouser, and Segger need to just let buyers check a box where they assume all liability and parts are just thrown in the mail and forgot about - something aliexpress is great at doing.
A quick search for "arm chip" on AliExpress shows lots of results, so I don't think your argument refutes anything I said.
>This is almost satirical.
That's all that needs to be said.
It's like comparing Unity and Godot. Unity is better in every single way but one, you have to license it from a very poorly ran company.
You don't "own" your games, they ship with black box spyware. The pricing for using it can change from day to day.
I swear the Unity C level employs a Magic 8 Ball and consults it for key management decisions.
If you need to edit the Unity Engine source code your looking at a secret additional licensing fee which is certainly unaffordable for hobbyist and most indies.
Vs Godot which is completely free under the MIT license.
Everything about the above can be said for ARM as well.
RISC-V is free for everyone to play with. If you think it sucks you can always fork it and jerryrig it to work on existing hardware.
If you have money you can even get custom hardware for your forked RISC-V.
I very much enjoyed reading this article, I'm optimistic in seeing what OPs students come up with. This is life changing technology that's essentially available to all.
> From that position, the difference between a ten cent part and a one dollar part is not a rounding error and it is not a detail you get to wave past on the way to the interesting discussion about encodings
Yet earlier:
> I pay anywhere from US $60 to US $200 to ship one dollar chips that people everywhere else get free shipping on
Seems to me that the difference between a 10c chip and a $1 chip are a rounding error when the shipping cost dominates so much?
> I can pick up H417s on the official WCH store on Aliexpress with free shipping and no verification hullabalu.
I think the point is that anyone can make these chips, so there are Chinese sellers who just throw them in a padded envelope and send them out without bothering with all the stuff "serious" vendors do. And because they're cheap enough, if doesn't matter if some get lost in the mail.
> The students I want to teach are in the same position, and so are the ones in Nigeria and Bangladesh
It does not take $60 to ship small sub $1 chips from Asia to Nigeria/Bangladesh. These two countries are all on global trade routes (both supply and demand) and the expensive last mile delivery costs are fairly low there too.
The typical bay area centric take has the following vibe:
1. I am among the group of most open minded people
2. I admit mistakes, but I don't change my view, that means I may make the same mistakes next time on a different concrete cases
3. Morally I am among the least corrupted
4. I work for the moderately morally questionable firms with nice paychecks, but my moral views are not tainted a bit
5. I never think on the other's perspectives
https://www.astralcodexten.com/p/the-foothills-of-bay-area-h...
My favorite bit, I think (along with the running gag of the constant use cases/connections that somehow pop up for Epstart’s founder):
> “Would you like to hear more about how copying AI tics helps me keep conversations going?”
> “Uh, sure - wait! No!” You break off and turn around as fast as you can.
If the other entries in the series are anywhere near as good, I’ll have some reading to do now.
Bangladesh is a country in Asia...
In my experience, the only demographic who complains about “Asia = east Asia” are people from South Asia, aka Indians/desis
So don't even try to find how expensive is bring these to Brazil. Even the $5 orders from JLCPCB become infeasible for hobbyists here due to all the roadblocks.
HN hasn't been Bay Area centric in years. Honestly, most comments and usership on the platform seems to now align with SWE culture in DACH and CEE.
Presumed RISC-V hate is a perfect example of that - the UCs and CSUs have been using RISC-V in their curriculum since the 2010s becuase Patterson is faculty at Cal and most CompArch courses in both systems have been using RISC-V as a result because 61a/b/c are often used as the benchmark curricula wise. An entire generation of Californian computer engineers have been RISC-V fluent as a result.
The hivemind assumption that HN's user base is "venture capital", "tech bro", "founders", and "Silicon Valley" is around 5 years out of date.
Anecdotally, the vast majority of younger (below 30) founders, engineers, VCs, and builders in the Bay have either not heard of HN or quit it within weeks due to toxicity.
I honestly do not get this at all. HN remains very US-centric to me, and especially centric to the mindshare of the Bay Area's IRL conversations, and apart from some takes on tech rights, does not really remind me of my experience in DACH.
>> HN remains very US-centric
Bay Area != US
The Bay Area is its own microcosm of culture and philosophy that diverges significantly from much of the US.
Not making a statement on how prevalent either are on HN, but Bay Area is very much not equivalent to the US.
The majority of HN's usership, posting, and comment activity occurs during peak EU work hours (3am-9am), stylistic patterns that are common for German-, French, and Polish-native speakers are increasingly prominent (eg. periods and spaces instead of commas in numbers, spacing between quotation marks and words, failing to use context clues to infer timezone), and the fact that IRL conversation topics in the Bay Area tech scene are entirely different from those on HN shows a massive divergence in userbase.
HN "Who wants to get hired" threads are a good example of that as well.
I'd recommend deep diving in the HN scrape dataset on HuggingFace [0]. The site has diverged heavily compared to 2018 or 2012.
[0] - https://huggingface.co/datasets/open-index/hacker-news
I like to encounter discussions about German digital health system or the German start up system or neo2. I've never seen them so I doubt it.
Also almost no debates about Polish stuff (Hello neigbours!)
fwiw, my experience is similar. hn has not been about startups, vc funding, or anything in that space for quite a while.
to paraphrase a classic, this place is like a memory of the forum we used to love, and the memory is fading.
Well, this place (wherever you are) is like a memory of the world we used to love, and the memory is fading... Definitely true too.
You can't expect a place tightly connected to a changing world to stay the same.
His criticisms are entirely valid, because why can't the the thing that has a free spec and will likely dominate that space ... also be good too? Can't we have all the nice things?
And while things has died down a lot in the past few years, there is a reason why I wrote the line.
"You do not criticise The Rusted Holy Grail and the Riscy Silver Bullet."
Though it feels a bit strange that "I have exceeded the allowed number of requests. (500 times)" when I first clicked the article and I'm pretty sure I don't share the ip of my self-hosted VPN with anyone.
Maybe I'm missing something important so far...
It definitely could have gone with a less abrasive tone (as entertaining as it is), so it's no wonder it's getting some pushback.
You have exceeded the allowed number of requests. Your Requests: 500. Request Limit: 500 per minute. Tip: Please wait 60 seconds before trying again.
A 3rd World Embedded Engineer Learns About Caching Generated HTML The Hard Way.
https://archive.md/9FaRC
This is especially good if one scopes out a family of ISAs that are ABI compatible such that one can compile down to a semi-pre-optimized portable IR, and just do the last bit per ISA.
And the approach you mentioned here:
> a family of ISAs that are ABI compatible such that one can compile down to a semi-pre-optimized portable IR, and just do the last bit per ISA
I think this is basically WebAssembly and PTX, and one may argue, Java bytecode. Yet look at how much efforts and time it took for WASM runtimes and JVMs to actually produce performant machine code (the "last bit per ISA" you mentioned) for just a couple of architectures! (e.g. X86 and ARM). And I wouldn't surprised if NVIDIA pour even more money on building optimization pipeline from PTX to each of their different uArchs.
I bet it would be pretty easy for a user to interoperate between 67 different drafts of the HTTP spec once they were all written, validated, and library implementations coded. But what would that Cambrian explosion of API revs actually get you?
I mean that is not even 10 page view per second. We are not living in 2006. Actually even in 2006 Apache with static page would have been able to handle that on a small VPS. And that is excluding CDN.
The 386 and 486 patent should have expired more than 20 years ago. No one tried to open source it. https://github.com/EI2030/Low-power-E-Paper-OS/blob/master/0... There were many companies that had clones in the early 90s, and I wonder whether any of them still have the rights to manufacture them.
" That is a better reason than elegance. and I want to tell Mr Grinberg, that the word priviledge he tosses around in his article also extends beyond the ISA depending on where you are in the world."
Grinberg is an emigre from Ukraine, which isn't the most privileged place in the world. In fact his research articles go deeper than the average software developer in Silicon Valley.
Edit: It also appears Nvidia might also have an x86 license: https://www.nvidia.com/en-us/drivers/uli-m6117c/
Also, https://www.tomshardware.com/pc-components/cpus/intel-licens... (Caveat: The startup is acquainted with the Intel CEO, so it's rare for them to grant the x86 license to non-buddies.)
"Intel provided Rosaic access to an unknown Atom-class core, which enables the company to build its own custom processors based on x86 general-purpose cores, according to the report. The renowned chipmaker plans to ship Rosaic register-transfer level (RTL) code for the Atom processor core, which will let the startup build its custom system-on-chip (SoC) both at Intel Foundry and elsewhere."
What's interesting is that a startup with limited funds would most likely seek a 32-bit x86 license if a) they don't need more than 4GB of RAM, and b), if they don't want to pay AMD for the 64 bit license add-on. :)
OpenFirmware came out of OpenSPARC and is also used by POWER too. Parts of it are used in ARM and RISC-V today (mostly DeviceTree, though arguably quite badly).
Nobody actually wants to make good cores for cheap. Nobody wants to make compatible systems unless forced to. That's why ARM and RISC-V are fragmented messes.
To do that they, at least, should still exist. For most of them this is not the case.
Your Requests: 500 Request Limit: 500 per minute
Your Requests: 500 Request Limit: 500 per minute
with no vpn
> Simply put, the things a high-end CPU needs are diametrically opposed to the things a small cost-saving microcontroller core needs.
> The conclusion he draws is that no single ISA can serve both ends, and that RISC-V fans are fooling themselves, in theory the premise is true. The conclusion does not follow, and I can show you why from three parts sitting on my desk as we speak.
> CH32V003. This is the cheap "RV32EC" with sixteen registers, no multiplier, no divider, machine mode only,
> CH32H417. A dual core MCU that is unmatched in performance to price point and is at the higher end of the MCU line
> Baochip. A VexRISC-V with an MMU built around a stack thats open from silicon to os Baochip-1x: A Mostly-Open, 22nm SoC for High Assurance Applications
Uh, which one of these is a datacenter server cpu? Or a workstation cpu? Or at least a developer laptop cpu? How about a Raspberry Pi 4 level SBC (supporting latest ubuntu and fedora releases, driving a display that runs a browser and plays video ...)
There's a lot of angry indignation but it seems obvious that Dmitry is quite right about this.
But I found this is where this blog post starts making a lot of sense:
> Has anyone tried adding an MMU to a Cortex-M? The physical tradeoffs are real, the difference is that with RISC-V, the ISA owner does not decide for you where that boundary must be drawn. If you want virtual memory on ARM you license a Cortex-A instead, which is a different core family, a different profile, a different negotiation, and a different royalty.
> Compare what happened with Baochip. The RISC-V privileged specification defines supervisor mode and Sv32 paging as optional things an implementation may provide. VexRISC-V is an open core, somebody added an MMU to it. bunnie built a chip around it and runs a microkernel with real process isolation on it
Yeah, that is a good point. We're still in the low-end specialty realm, but that is real interesting advantage for RISC-V, a good reason for it to exist.
As for shipping to Trinidad and Tobago ... this post is trying too hard to turn this into moral issue, but it seems a bit random (OrangePi cost $30 and shipped free? you can also get arm-based and stuff from the same places), and the vast majority of people don't live on semi-remote islands, it doesn't make sense to consider this kind of accessibility above all else, and it's strange to blame Dmitry for not thinking of you here.
I read the "They Should Have Known Better" article and forgot it. I've seen this before. I know it's hot air and does not matter, and I can't afford to worry about things that don't matter.
When I say I've seen this before, I'm talking about ancient history: controversies so old and so laughable that they've been forgotten. When, for example, AMD handed the world AMD64/X86_64, the same things were said: fragmentation, legacy+flawed ISA, etc. That has not aged well, and "They Should Have Known Better" won't either.
The "fragmentation" argument has no merit. The jumble of extension names and profiles in RISC-V are, in fact, direct evidence that RISC-V is succeeding: it's the RISC-V ecosystem aggressively, collaboratively and successfully tackling pain points and solving them. This is what RISC-V is supposed to be doing, and it's doing it, and empires are being built on it.
Take this part: "The existence of CLIC and various proprietary 'fast IRQ' / auto-stacking extensions is an additional indictment."
CLIC is miraculous. It's an advanced embedded interrupt controller, and it's wonderful: it brings the equivalent of ARM's NVIC to RISC-V, except better. You can implement an extremely efficient scheduler that guarantees deadlock-free concurrency: bare-metal, real-time, hardware-accelerated "Fearless Concurrency," on an MCU with no RTOS![1] Its appeal is so great that, despite still being a draft spec, the leading RISC-V MCU designers are adopting it. Espressif's ESP32-S31 has it, for example. The chaotic emergence of this awesome thing is what is condemned as an "indictment."
Speaking of ESP32-S31, it's going to be a monster when silicon becomes available in quantity. This RV Embedded writing mentions MMUs a lot. Guess what? The S31 has an Sv32 MMU. It can run Linux. Not μClinux. Real Linux. It's already been done twice (that I know of) on the Espressif eval boards. People like Armstrong Subero are going to change the world with it.
That's the froth of RISC-V. The ground is shaking, and the peanut gallery of ISA wizards has no power over it. In a few years, after RISC-V has lain waste to our world of proprietary ISAs and Western IP regime rent seeking, "They Should Have Known Better" will look as silly to everyone as it already looks to me.
[1] https://rtic.rs/2/book/en/
https://rvembedded.com/products/project-lab/
Definitely interested!
Does anyone have an archive?
Same reason the southern accent has overlaps with west African dialects.
Some serious stuff he builds on top of those chips.
“I am, somehow, less interested in the weight and convolutions of Einstein’s brain than in the near certainty that people of equal talent have lived and died in cotton fields and sweatshops.”
― Stephen Jay Gould
Edit: y’all really don’t like being told you should care about other people, huh?
Is that really your take?
Frankly I'd rather be told that than the other common but tired SV-resident take of "just hustle, bro, stop sleeping, hustle hustle hustle. Learn to code, take loans from friends and family. Doesn't matter that you're born in a shithole, I was born in a median family myself, we only had one car and we rented our house!!! Just gotta work for it, everybody can achieve it. Those who don't, are clearly not working hard enough."