Can AI design circuit boards yet?

The models are excellent at doing maths, and excellent at thinking of fine details, but the design that was ultimately landed on was pretty excessive with lots of total overkill, which was met with lots of the familiar "Yeah, you're totally right, we don't need to do that".

5.6 did make a really nice BOM though, which even included quick reference explainers for what each part did. Pretty fancy.

We'll see when Astra comes around if it catches all these strange/useless choices.

That the table contains what seems to be absolute numbers for score, cost/task, time/task and output tokens, makes it seem like they've only made one run for each task/model combo, but that can't be right, right? I don't see any mentions of how many times they run each task, so if it's just one run per task/model, isn't this more noisy than useful?

I have yet to order any or program it, but it was enough to make me push on with a PCB art project for ST-style guitar pickguards - no netlist, no problems.

I'm also foolishly toying with NeXTBus dev boards for the Cube. Is it cursed? Probably. https://github.com/itomato/NeXTBus-Dev-Board

> A real capacitor makes the task more interesting. A ceramic part may provide much less than its advertised capacitance once it has voltage across it. Parts have tolerances. Adding more capacitance costs more, takes up space and makes the rail slower to recharge when the power returns. A design that works with nominal values can fail with the parts that arrive.

It sounds like from a reasonable reading of the benchmark post that there's some things that are being tested that are assumed to be criteria that you expect the models to intuitively find those things to be important (i.e. the stuff about working on parts that have tolerances etc.). If that's so, then this really feels like mostly an exploration of whether an LLM has a good understanding of unstated constraints and has an appropriate in distribution set of priors that would be able to form models where it's reasonable to design on those lines.

It's hard to tell whether this is a problem though as the methodology is imprecise.

If you're spending time on evals against your own product, I'd be super curious to see how far you can get to by using a top tier model to produce generalized instructions for lower tier models. E.g. in a loop: "This eval missed X. what's the simplest single instruction that would have helped this session consider that as necessary that can benefit all future runs. Stick that in AGENTS.md and retest."

I have no experience and I'm slowly failing forward with the help of YouTube, KiCad and patience.

I've had three rounds of PCB's from an online supplier, only to discover issues related to my own understanding of the components in each version.

In my latest iteration I've been leaning on some standard models (Gemini and Claude) and they have inspected my schematics and spotted some errors and instructed me on how to address them, as well as advised on how to make use of some components I wasn't aware I needed.

What I will say... they didn't design anything, I've done that myself, but they have been a good tool to bounce ideas off of.

Time will tell if I will get something usable this time around!

If anyone wants to try an early beta, reply with your CircuitLab username and I'll get you set up. We know have a lot more to do, but would love some feedback on this early version!

But I started like others, I would build manually, then run drc then sleep on it and check again and ask an llm to double check for me then order. Llms catch quite a few things but like with code like to make things more complicated than that have to be.

Super excited to see real world feedback added into the agent loops we have gotten used to working with. Could you let the model print and test the circuit boards it is prototyping with a jig?

I'm guessing that this is due to a lack of RL and data.

Recent models can generate mostly competent schematics if you're using well known parts, feed them data sheets (and you _must_ feed them the errata too) and it's not too complex. Any complexity analog or RF, everything falls down quickly if you know what you're looking at. Maybe Astra will do better? There's still so much implicit knowledge that a good designer (not me by a long shot, but I know a little) will bake into a board, and even as cheap as JCLPCB is now, you don't want to have to spin a half dozen revs because Claude or Codex hallucinated. It will be genuinely interesting to see what happens on this front.

It will use the part datasheets and decent EE logic to cross reference pins and parts and polarities and generally check that SMD caps and resistors have realistic specifications for their footprint, switching regulators and communication ICs are configured correctly (e.g. when you have resistor settings for an ethernet PHY indicating 100Base-T and RMII, you also won't need TX/RX 2 and 3 and two clocks and a COL net, which it would check), all nets are named and linked correctly, buses have the correct and consistent termination, and so on.

It's game over once AI figures out autorouting.

The next pain-point is sourcing the components from Digikey, LCSC, etc., and finding suitable substitutes if necessary.

Of course this assumes the LLMs can already read datasheets because that's the biggest pain-point in designing electronics. It's like filling out tax forms.

Finally it would be great if LLMs could extract simulation models from datasheets!

All robots designed by robots.

Likely a crazy youtuber first

[1] https://www.schematik.io/

Frankly, I am surprised that it isn't already a solved problem, as we've had silicon compilers, for many years, and I always figured that IC design is more difficult than PCB.

I’ve had similar results asking AI to design 3D models for 3D printing.

“Coach me on optimizing error on my printer”… helps.

“Build me a print ready file to these specs.”… it’s like a drunk cat attacked my computer. Just confidently puts out total nonsense.

Anyway... the posed question reminds me of an anecdote I cannot find because Google is contaminated to hell and beyond, some researchers a decade ago let a machine-learning algorithm loose on an FPGA, and it "found" a design that worked but made no sense, because it exploited unique physical features of this specific chip.