ao486: x86-compatible Verilog core implementing all features of a 486 SX (2014)

It’s a neat core, but z386 is where the action is right now (https://github.com/nand2mario/z386_MiSTer). Interestingly this core doesn’t output a proper analogue signal. I always wondered why until I recently tried to implement a real EGA pixel clock on the PCXT EGA core. Basically, video cards with dual (or more) pixel clocks are not realistic on MiSTer. The PLLs are there, but once you get too many clock sources the routing becomes quickly impossible. MiSTer framework’s pipeline also forces pixel clocks tied directly to video output (for good reason) and switching that clock at runtime gets very tricky.