Show HN: A Project Oberon System version running on RISC-V instead of RISC-5

thisislife2•about 1 hour ago

Love your commitment to this. You are doing excellent work to keep Wirth's computing spirit alive. Oberon's philosophy ( https://people.inf.ethz.ch/wirth/Oberon/Oberon07.Report.pdf ) is beautiful for the power it hides behind its simplicity and I wish it was a more popular language ...

Rochus•about 1 hour ago

Thanks. Though I migrated the code from Oberon-07 to Oberon 90 (so I could compile it with my OP2 version) and currently I even migrate it to my forthcoming Micron language. The Project Oberon System is very well suited for these kinds of experiments.

cxr•about 1 hour ago

Readers encountering this project for the first time should be aware that the earlier Oberon-on-RISC-V project <https://github.com/solbjorg/oberon-riscv> (HN discussion: <https://news.ycombinator.com/item?id=25497002>) exists and was already discussed on the mailing list:

<https://lists.inf.ethz.ch/pipermail/oberon/2026/017161.html>

tosh•17 minutes ago

what does RISC-V instead of RISC-5 mean?

tosh•16 minutes ago

https://en.wikipedia.org/wiki/RISC5

clbrmbr•about 2 hours ago

Would it be practical to have the ESP P4 self-host?

Rochus•about 2 hours ago

The ESP32-P4 is actually my target platform. I have a cross-compiler toolchain based on my own OP2 compiler version (see https://github.com/rochus-keller/op2/) which makes it easier to migrate. The Project Oberon System is an "intermezzo" for my actual goal, the Oberon System 3; the latter can also run my OP2 version and would thus be able to self-host. I didn't try yet to run OP2 under the Project Oberon System, but with some patience I assume it is feasible.

berkeleynerd•about 1 hour ago

This is super interesting Rochus. Are you targeting Oberon System 3 in particular because it adds tcp/ip networking support? In my opinion that would make it a much more interesting system to kick the tires on, if so!

Rochus•about 1 hour ago

Thanks. I rather do it as a "proof of concept" to demonstrate that the Oberon System is a (hopefully) great fit with today's microcontroller boards, particularly the Olimex ESP32-P4-PC, which even has a HDMI connector. I already migrated the system to the Raspi Zero 2 which is yet another lean target, but actually oversized for the Oberon System, which doesn't even require an MMU (not to mention multiple cores). The networking support code is currently not used, because it would require yet another (pretty complex) driver. But it might be feasible (with a lot of patience) to implement it directly on the board as soon as the system and compiler run stable on it.

OCTAGRAM•about 2 hours ago

> The whole system runs on a low-cost development board (Xilinx Spartan-3 by Digilent, with 1 MB of static RAM)

If somebody wants their FPGA work to be available, they better choose MiSTer FPGA from the beginning. Costlier, but way more likely to be found around.

Rochus•about 2 hours ago

The availability of the board to run Wirt's system was an issue pretty soon. There were even people who offered their own boards to fill the gap (e.g. https://web.archive.org/web/20160831063355/http://oberonstat...).

My system version instead runs on RISC-V, so no custom FPGA implementation, currently on an emulator, but eventually on the ESP32 (which has a much better availability).

Joker_vD•about 2 hours ago

> they better choose MiSTer FPGA from the beginning.

Well, the MiSTer project was yet 4 years from being launched back in 2013 when the RISC-5 was implemented in FPGA, so I hope you'd excuse Wirth from not choosing it.

Rochus•about 1 hour ago

And shortly after Wirth launched his RISC-5 system, the original FPGA board went out of production.

pjmlp•about 1 hour ago

Which most likely wasn't predictable for him.

FPGAs were never that maker friendly, due to the whole ecosystem.

Show HN: A Project Oberon System version running on RISC-V instead of RISC-5

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