Sandia National Labs SA3000 8085 CPU

There have been a number of rad-hard SPARC chips from different vendors tthat have flown along the way, and I know Frontgrade/Gaisler currently sells a SPARC v8 version, which isn't that far behind the 'state of the art' as the e5500 based PPCs from BEA (at least as far as state of the art in space rated, rad-hard processors goes...it's a conservative market). Quite a few rad-hard ARMs out there farther down the performance curve.

Frontgrade also advertises a rad-hard RISC-V, as does Microchip (a PIC64 variant), that I know nothing about, but seems like an inevitable next step. Seems like you could grab some Xilinx rad-hard FPGA and bobs your uncle.

what scale of radiation do such hardened designs target?

Wow, until you posted this I thought Moog was just a synthesizer company. And a bit of an odd one at that based on how I saw that synth presented.

You don't need much calculation power to manage a 30-min ballistic trajectory.

The inertial navigation system is the very crazy part, along with the nuclear fusion warhead design itself.

https://youtu.be/AazmxNs5kmE?is=2LE2q3rBSWDyTs7j

Like others have mentioned, 50k small CPUs like 8085 can be made in a single production batch (i.e. a small basket containing silicon wafers, which passes through all manufacturing steps), so a number like this is likely to be the minimum amount that can be produced.

The customer would order this minimum quantity, and most of it will probably be kept as spares.

I assume the tooling and process are such that it’s a one-time thing, as in, this is the most of these chips that we could ever possibly need for all time. They’re not going to be able to spin up the same fab and build the same chips the same way again in the future whether that’s 5 or 50 years in the future. Given the long lifespans of military systems, it’s maybe not so crazy.

That number was probably shaped by minimum production-run requirements, alongside the need for software development units, along with other factors, like the use in Trident II and other quests we may not know about.

I also am curious about that statement. Seems something got mixed up between the quantity of the full run and the quantity for the probe.

This is standard semiconductor manufacturing jargon.

"Substrate" here refers to the silicon wafer on which the integrated circuits are made, which at the end of the manufacturing process is cut into individual chips, which are then packaged as CPUs in this case.

An epitaxial wafer is a wafer on which epitaxial growth has been done before the rest of the manufacturing process. The wafers are cut from a huge crystal that has been grown from molten silicon. Initially they have a uniform concentration of doping impurities throughout their volume.

Epitaxial growth means that an extra layer of silicon is grown on the wafer and the growth is done in such a manner that all the layer is a single crystal and its lattice continues the crystal of the wafer, without interface defects.

The purpose is to have a different concentration of impurities in the extra layer, compared with the base wafer. N-on-n+ means that the initial wafer contained N-doping impurities, e.g. antimony, in a very high concentration (+), so that its electrical resistance would be minimum, while the "n" epitaxial layer also contains an N-doping impurity, e.g. phosphorus, but in a much lower concentration, so that it has a high electrical resistivity.

Both the fabrication of silicon wafers and the epitaxial growth are typically done by other companies than those that make integrated circuits, so the IC maker, or a silicon foundry like TSMC, buys epitaxial wafers according to a certain specification and they use them as the starting material in their manufacturing process.

"Latchup control" is a term specific to CMOS integrated circuits. In CMOS there exists a parasitic thyristor (a.k.a. SCR) composed of 2 parasitic bipolar transistors. If the parasitic thyristor turns on, it applies a short-circuit on the power supply, causing a huge electrical current spike, which normally destroys the integrated circuit, perhaps also other things if the power supply is not protected against short circuits.

In order to prevent the latchup of the parasitic thyristor, the structure is modified in various ways to reduce the gain of the parasitic transistors. If the gain is low enough, the thyristor cannot turn on.

Using a simple n substrate (which is cheaper) results in a high gain for the parasitic pnp bipolar transistor. Using an epitaxial n-on-n+ wafer reduces the gain of the pnp, lowering the probability of latchup.

Guard rings around transistors (which are made by diffusing certain doping impurities and then possibly also covering the diffused ring with a polysilicon or metal ring) have various purposes, typically related to preventing the electrical breakdown of the transistors at lower voltages than intended. This is especially important for radiation-hardened devices, because the most frequent effect of the passage of a ionizing particle through the semiconductor would be to generate mobile charge carriers that could cause the electrical breakdown of a transistor.

"Hardened oxide" is a more ambiguous term, but I assume that here it refers to high-quality oxide, i.e. which has a high value for the electrical field that can be sustained without electrical breakdown.

Excellent find. And yes, obviously this is slop. 106 rad is exactly nothing for nuclear usage.