IBM debuts sub-1 nanometer chip technology

For silicon, the gate length of a FET has a lower limit somewhere between 10 nm and 15 nm.

The current CMOS manufacturing processes have not reached the limit yet. For making smaller transistors, a transition to other semiconductor materials will be necessary.

The vertical thicknesses of various layers may be of only a few nanometers or even of a fraction of a nanometer, but that does not matter directly for the circuit density.

The supposed node size refers to horizontal dimensions, not to vertical dimensions.

Vertical dimensions of around 1 nanometer or less could be achieved already many decades ago, because they depend on growth speed and on time, not on lithography, like the horizontal dimensions.

The industry should have stopped decades ago to talk about the "size" but they should have characterized a CMOS process by its density, e.g. in logic gates per square mm.

However, an actual concrete number would be disliked by marketing, because they could no longer claim that their "1 nm" process is better than the "2 nm" process of another vendor, if their density is not really better.

We care about PPA (power, performance, area) and not how large or not-large features actually are. Comparing gate lengths between a 1980s planar transistor and a 2010s 3D FinFET or GAA transistor is obviously nonsense, the relatively aligned node names of the industry actually do make sense as a shortcut here.

Different companies measure it differently too. This was a while ago, but I remember reading that Intel 10nm was more or less close to TSMC 7nm. I'm sure this is still true to varying degrees.

Once you make the gate of a transistor small/thin enough, quantum effects take over. Electrons will randomly teleport into and through the gate causing the transistor to conduct when it shouldn't. I don't have numbers to hand, but it's on the order of a few atoms wide. There's really nothing that can be done about it either, as far as we know. Electrons just aren't physical objects at this scale, you can't simply exclude them from any given volume of space. The electron wave function will simply just appear wherever it wants (within the electron probability cloud). The only way to stop it is to make your insulating junction thicker than the probability cloud.

https://en.wikipedia.org/wiki/Landauer%27s_principle

Beyond that, engineering a quark-gluon plasma as a processor? I'd watch that Star Trek episode. (we might fantasize about stuff like that but we're roughly monkeys smashing rocks together in a cave vs. building an iPhone sort of gap away from that kind of thing unless somebody has a really good idea)

Broadly speaking yes, this is the business model. IBM has been at this for many years with technology transfers, licensing agreements, support and other arrangements. Rapidus, Samsung, GlobalFoundries, ST, SMIC, AMD, etc. have all used IBM R&D work at various times for various nodes and products.

The cutting edge of semiconductors is a writhing mass of copulating tapeworms, and IBM lives deep inside that ball. For IBM, what this means is that when you buy one of the ASML machines to make products with this process, you'll pay IBM for the knowledge and support to actually get it working, or give them a cut, or something else, TBD, as circumstances warrant.

Why? What's their real size?

Not doubting you, just trying to understand and also trying to assess how exaggerated the marketing is.

So many breakthroughs in hard drives, chips, transistor density, and other aspects of computing have come out of their labs.

Great to see them continuing to innovate.

But, yeah, usually they partner and license. Over the years, they've spun off more and more of their hardware businesses.

1 Å = 100 pm. 1 pm = 0.01 Å.

1 angstrom = 0.1 nanometers, 100 picometers

1 nanometer = 10 angstroms, 1000 picometers