Running Doom on Our Custom CPU and Going Viral

Hi, I didn't follow any specific guide on this, but asked ChatGPT about the bare minimum environment needed to run DOOM. From there, I figured out how to execute the instructions using a switch-case and how to make a custom syscall to trigger rendering.

I made a post a while back that details the entire process: https://www.reddit.com/r/EmuDev/comments/1t1or4j/doom_runs_o...

If you don't want to delegate the fun of learning to an LLM, here's how I've built a RV64IM simulator in C in a weekend. All you need is an opcode table, the RISC-V specs and to implement each instruction; the good thing of RISC CPUs is that instructions are very simple (i.e. pretty much everything is a variation of `dest = src1 OP src2`) and memory instructions are dedicated. The other cool thing is that there are no "flags". Start with the base instruction set, then you can add M on top later. 64-bit support requires just a handful more instructions to zero/sign extend from 32-bit.

Then, wire your simulator to https://github.com/riscv-software-src/riscv-tests, and there you have an official test suite. When everything passes, you have a fully-compliant RISC-V CPU. You can at this point tell GCC or Rust or your favourite language to compile to RV32IM and see it run on your simulator. It's a very gratifying process.

If you get at this stage, you might want to use the ecall instruction to hard-code I/O operations such as "read from stdin" or "print a character", and there you have a sandboxed CPU that you can target with your favourite programming language. Make it run DOOM (start with https://github.com/ozkl/doomgeneric and see which I/O do you need), or turn it into a toy game console; the sky's the limit.

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Here's a copy-paste of the list of resources I have saved in my notes:

- https://github.com/libriscv/libriscv A very fast RISC-V VM with sandboxing of memory and syscalls.

- https://luplab.gitlab.io/rvcodecjs/ RISC-V Instruction Encoder/Decoder

- https://www.cs.sfu.ca/~ashriram/Courses/CS295/assets/noteboo... Reference card

- https://cs.brown.edu/courses/csci1952y/2024/assets/docs/risc... Spec

- https://riscv-software-src.github.io/riscv-unified-db/manual...

- ABI: https://lists.riscv.org/g/tech-psabi/attachment/61/0/riscv-a...

Good luck!

Making a particularly good core is hard. Making a core to the minimum risc-v spec is what you do in a single college course. It's what the ISA was designed for.

It's a custom implementation of an existing architecture

The *architecture* is RV32I_Zmmul which is unambiguously neither new nor custom.

What you describe (the specific implementation details of a core) is *microarchitecture*. In this case clearly a lot of work was done and it is cool, but the *architecture* is indeed RV32I and not custom

I was not undermining anything. I was helping others find the info I sought and took a while to find. This is why i left my comment. Everyone has their own interests. As an example, my thoughts were "whoa... a new architecture... did they write a new compiler or rewrite doom in assembly?" and for that "it is rv32i" would have been a quick answer.